This application claims priority to Chinese Patent Application No. 200910197450.3, filed Oct. 20, 2009 in the People's Republic of China, commonly assigned herewith and incorporated in its entirety by reference herein for all purposes.
The present invention relates to a CMOS image sensor, and more particularly, to a CMOS imaging sensor using a capacitive coupled readout structure.
In general, a semiconductor based image sensor is a solid state imaging device having an array of pixel cells arranged in columns and rows. Each pixel cell includes at least a photo sensing element and other active components that convert an amount of incident light to an electrical (voltage or current) signal. Image sensors are classified into charge coupled devices (CCDs) and complementary metal oxide semiconductor (CMOS) image sensors (CISs). CCDs are often employed for image acquisition and enjoy a number of advantages, which makes it the incumbent technology, particularly for small size imaging applications. CCDs are also capable of large formats with small pixel size and they employ low noise charge domain processing techniques. However, CCD imagers also have limitations. For example, they are susceptible to radiation damage, they exhibit destructive read out over time, they require good light shielding to avoid image smear, and they have a high power dissipation for large arrays. Additionally, while offering high performance, CCD arrays are difficult to integrate with CMOS processing, in part due to a different processing technology and to their high capacitances, complicating the integration of on-chip drive and signal processing electronics with the CCD array. While there have been some attempts to integrate on-chip signal processing with the CCD array, these attempts have not been entirely successful. CCDs also transfer an image by line charge transfers from pixel to pixel, requiring that the entire array be read out into a memory before individual pixels or groups of pixels can be accessed and processed, which takes time. CCDs may also suffer from incomplete charge transfer from pixel to pixel during charge transfer, which also results in image smear.
Because of the inherent limitations in CCD technology, CMOS image sensors have become the technology of choice thanks to their capability of integrating advanced signal processing capabilities on the same die, thus simplifying the system design and reducing the overall system cost.
The advantages of CMOS image sensors over CCD imagers are that CMOS image sensors have a low voltage operation and low power consumption; CMOS image sensors are compatible with integrated on-chip electronics (control logic and timing, image processing, and signal conditioning such as A/D conversion); CMOS image sensors allow random access to the image data; and CMOS image sensors have lower fabrication costs as compared with the conventional CCD since standard CMOS processing techniques can be used. Additionally, low power consumption is achieved for CMOS image sensors because only one row of pixels at a time needs to be active during the readout and there is no charge transfer (and associated switching) from pixel to pixel during image acquisition. On-chip integration of electronics is particularly advantageous because of the potential to perform many signal conditioning functions in the digital domain (versus analog signal processing) as well as to achieve a reduction in system size and cost.
A CMOS image sensor circuit includes a focal plane array of pixel cells, each one of the cells including either a photodiode overlying a substrate for accumulating photo-generated charge in the underlying portion of the substrate. A readout circuit is connected to each pixel cell and includes at least an output field effect transistor formed in the substrate and a charge transfer section formed on the substrate adjacent the photodiode having a sensing node, typically a floating diffusion node, connected to the gate of an output transistor. The imager may include at least one electronic device such as a transistor for transferring charge from the underlying portion of the substrate to the floating diffusion node and one device, also typically a transistor, for resetting the node to a predetermined potential level prior to charge transfer.
CMOS image sensors are classified into 3T type, 4T type, and the like according to the number of transistors contained in a pixel cell. The 3T type CMOS image sensor includes one photodiode and three transistors, and the 4T type CMOS image sensor includes one photodiode and 4 transistors.
In a conventional CMOS image sensor, the elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) transfer of charge to the floating diffusion node accompanied by charge amplification; (4) resetting the floating diffusion node to a known state before the transfer of charge to it; (5) selection of a pixel for readout; and (6) output and amplification of a signal, which is representative of the illumination level recorded at the pixel. The charge at the floating diffusion node is typically converted to a pixel output voltage by a source follower output transistor. The photosensitive element of a CMOS image sensor pixel is typically a depleted p-n junction photodiode. For photodiodes, image lag can be eliminated by completely depleting the photodiode upon readout. More detailed description of the CMOS image sensor is provided in U.S. Pat. No. 6,654,057 (Rhodes), which is incorporated herein by reference.
FIG. 1A is a layout of a 3T CMOS image sensor device 100 according to the prior art. The 3T CMOS image sensor device 100 includes a photodiode 102, an n+ floating diffusion region 103, a reset transistor 104, a source follower transistor 106, and a row select transistor 108. Contacts 114 and a conductive layer 115 couple photodiode 102, reset transistor 104, and source follower transistor 106. The n+ floating diffusion region 103 is interposed between the photodiode and the reset gate electrode of the reset transistor 104. The conductive layer 115 connects the n+ floating diffusion region 103 to the gate electrode of the source follower transistor.
FIG. 1B is a schematic diagram of a pixel cell 150, which is the electrical equivalent circuit of the 3T CMOS image sensor device 100 shown in FIG. 1A. The pixel cell 150 includes a photodiode 152 that receives incident light 153. The incident light generates electrons that are captured in the depletion capacitance of the reverse biased photodiode 152. The photodiode 152 is reversed biased by a reset transistor 154 to a predetermined reset voltage level 165. The reset transistor is controlled by a reset signal 155. The charge accumulated at the depletion capacitance of the photodiode at a node 160 changes the predetermined reset voltage. The voltage signal at node 160 is then buffered by a source follower transistor 156. The output of the source follower transistor is connected to a pixel select transistor 158 for reading out the voltage signal of the pixel cell at node 160. Pixel select transistor 158 is controller by a select signal 159. All pixel cells in a given column share a common signal bus output 167.
FIG. 1C is a partial cross-sectional view 170 of the 3T type CMOS image sensor layout shown in FIG. 1A. Photodiode 171 is formed by a N− doped region 172 and a P+ doped region 173 as known in the art. The n-type doped region 172 is defined by a mask and formed by implanting n-type dopants. N-type dopants such as arsenic, antimony, or phosphorous may be employed. The p-type doped region 173 is also formed by conducting a masked implantation with a dopant of p-type ions over the implanted n-type region 172. P-type dopants such as boron, beryllium, indium, or magnesium may be employed. An N+ doping diffusion 174 forms the floating diffusion region 174 (103 in FIG. 1A), which is then etched to form contact 150. In general, the contact in the floating diffusion (FD) area is a major source of dark current because of the damage that may be caused during the process of forming the contact. In order to provide the ohmic contact for the contact 150, an n+ region is formed on the area where the contact will be formed. The n+ region is formed by heavily implanting n-type dopants. This heavy implantation process can noticeably damage the silicon crystal of the substrate. The silicon crystal may also be damaged when a plasma etch process is performed to obtain a via opening for the contact. FIG. 1C shows the n+ doping induced crystal defects and also the contact etch induced crystal defects to the silicon crystal, and that the crystal defects cause an increase of the junction leakage. If the junction leakage is large, the floating diffusion region is not able to preserve an amount of charge from the photodiode, and the amount of charge may be lost even in the dark and results in a poor signal-noise ratio (SNR).
FIG. 2 is a simplified layout of a 4T CMOS image sensor device 200 according to the prior art. The 4T CMOS image sensor device 200 includes a photodiode 202, a transfer transistor 204, a reset transistor 206, a source follower transistor 208, and a row select transistor 210. The 4T CMOS image sensor device 200 uses the additional transfer transistor 204 to avoid having a contact in the photodiode, as in the case of the 3T CMOS image sensor device 100. By not having a contact in the photodiode, the 4T CMOS image sensor device generally provides better performance especially in the dark noise reduction over the 3T CMOS image sensor device. The transfer transistor serves to separate the photodiode from the potential sensing floating diffusion (FD) region.
Thus, a 4T CMOS image sensor device can reduce some of the junction leakage associated with the contact formation in the 3T CMOS image sensor device by not having to form a contact on the photodiode. However, this comes at the cost of an increase in the image sensor size because of the additional transfer transistor. It would be desirable to reduce the dark current and at the same time shrink the pixel cell size by reducing the number of active elements such as transistors.